retdec
Public Member Functions | Protected Member Functions | Static Protected Attributes | List of all members
retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl Class Reference

#include <arm_impl.h>

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Public Member Functions

 Capstone2LlvmIrTranslatorArm_impl (llvm::Module *m, cs_mode basic=CS_MODE_ARM, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
virtual bool isAllowedBasicMode (cs_mode m) override
 
virtual bool isAllowedExtraMode (cs_mode m) override
 
virtual uint32_t getArchByteSize () override
 
- Public Member Functions inherited from retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >
 Capstone2LlvmIrTranslator_impl (cs_arch a, cs_mode basic, cs_mode extra, llvm::Module *m)
 
virtual ~Capstone2LlvmIrTranslator_impl ()
 
virtual void setIgnoreUnexpectedOperands (bool f) override
 
virtual void setIgnoreUnhandledInstructions (bool f) override
 
virtual void setGeneratePseudoAsmFunctions (bool f) override
 
virtual bool isIgnoreUnexpectedOperands () const override
 
virtual bool isIgnoreUnhandledInstructions () const override
 
virtual bool isGeneratePseudoAsmFunctions () const override
 
virtual void modifyBasicMode (cs_mode m) override
 
virtual void modifyExtraMode (cs_mode m) override
 
virtual uint32_t getArchBitSize () override
 
virtual TranslationResult translate (const uint8_t *bytes, std::size_t size, retdec::common::Address a, llvm::IRBuilder<> &irb, std::size_t count=0, bool stopOnBranch=false) override
 
virtual TranslationResultOne translateOne (const uint8_t *&bytes, std::size_t &size, retdec::common::Address &a, llvm::IRBuilder<> &irb) override
 
virtual const csh & getCapstoneEngine () const override
 
virtual cs_arch getArchitecture () const override
 
virtual cs_mode getBasicMode () const override
 
virtual cs_mode getExtraMode () const override
 
virtual bool hasDelaySlot (uint32_t id) const override
 
virtual bool hasDelaySlotTypical (uint32_t id) const override
 
virtual bool hasDelaySlotLikely (uint32_t id) const override
 
virtual std::size_t getDelaySlot (uint32_t id) const override
 
virtual llvm::GlobalVariable * getRegister (uint32_t r) override
 
virtual std::string getRegisterName (uint32_t r) const override
 
virtual uint32_t getRegisterBitSize (uint32_t r) const override
 
virtual uint32_t getRegisterByteSize (uint32_t r) const override
 
virtual llvm::Type * getRegisterType (uint32_t r) const override
 
virtual bool isControlFlowInstruction (cs_insn &i) const override
 
virtual bool isCallInstruction (cs_insn &i) const override
 
virtual bool isReturnInstruction (cs_insn &i) const override
 
virtual bool isBranchInstruction (cs_insn &i) const override
 
virtual bool isCondBranchInstruction (cs_insn &i) const override
 
virtual llvm::Module * getModule () const override
 
virtual bool isSpecialAsm2LlvmMapGlobal (llvm::Value *v) const override
 
virtual llvm::StoreInst * isSpecialAsm2LlvmInstr (llvm::Value *v) const override
 
virtual llvm::GlobalVariable * getAsm2LlvmMapGlobalVariable () const override
 
virtual bool isCallFunction (llvm::Function *f) const override
 
virtual bool isCallFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::BranchInst * isInConditionCallFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::Function * getCallFunction () const override
 
virtual bool isReturnFunction (llvm::Function *f) const override
 
virtual bool isReturnFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::BranchInst * isInConditionReturnFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::Function * getReturnFunction () const override
 
virtual bool isBranchFunction (llvm::Function *f) const override
 
virtual bool isBranchFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::BranchInst * isInConditionBranchFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::Function * getBranchFunction () const override
 
virtual bool isCondBranchFunction (llvm::Function *f) const override
 
virtual bool isCondBranchFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::BranchInst * isInConditionCondBranchFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::Function * getCondBranchFunction () const override
 
virtual bool isAnyPseudoFunction (llvm::Function *f) const override
 
virtual bool isAnyPseudoFunctionCall (llvm::CallInst *c) const override
 
virtual llvm::GlobalVariable * isRegister (llvm::Value *v) const override
 
virtual uint32_t getCapstoneRegister (llvm::GlobalVariable *gv) const override
 
virtual bool isPseudoAsmFunction (llvm::Function *f) const override
 
virtual bool isPseudoAsmFunctionCall (llvm::CallInst *c) const override
 
virtual const std::set< llvm::Function * > & getPseudoAsmFunctions () const override
 
- Public Member Functions inherited from retdec::capstone2llvmir::Capstone2LlvmIrTranslator
virtual ~Capstone2LlvmIrTranslator ()=default
 

Protected Member Functions

virtual void initializeArchSpecific () override
 
virtual void initializeRegNameMap () override
 
virtual void initializeRegTypeMap () override
 
virtual void initializePseudoCallInstructionIDs () override
 
virtual void generateEnvironmentArchSpecific () override
 
virtual void generateDataLayout () override
 
virtual void generateRegisters () override
 
virtual uint32_t getCarryRegister () override
 
virtual void translateInstruction (cs_insn *i, llvm::IRBuilder<> &irb) override
 
llvm::Value * getCurrentPc (cs_insn *i)
 
virtual llvm::Value * loadRegister (uint32_t r, llvm::IRBuilder<> &irb, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::THROW) override
 
virtual llvm::Value * loadOp (cs_arm_op &op, llvm::IRBuilder<> &irb, llvm::Type *ty=nullptr, bool lea=false) override
 
virtual llvm::Instruction * storeRegister (uint32_t r, llvm::Value *val, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::SEXT_TRUNC_OR_BITCAST) override
 
virtual llvm::Instruction * storeOp (cs_arm_op &op, llvm::Value *val, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::SEXT_TRUNC_OR_BITCAST) override
 
llvm::Value * generateInsnConditionCode (llvm::IRBuilder<> &irb, cs_arm *ai)
 
llvm::Value * generateOperandShift (llvm::IRBuilder<> &irb, cs_arm_op &op, llvm::Value *val)
 
llvm::Value * generateShiftAsr (llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n)
 
llvm::Value * generateShiftLsl (llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n)
 
llvm::Value * generateShiftLsr (llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n)
 
llvm::Value * generateShiftRor (llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n)
 
llvm::Value * generateShiftRrx (llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n)
 
uint32_t sysregNumberTranslation (uint32_t r)
 
virtual bool isOperandRegister (cs_arm_op &op) override
 
virtual uint8_t getOperandAccess (cs_arm_op &op) override
 
void translateAdc (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateAdd (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateAnd (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateB (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateBl (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateCbnz (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateCbz (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateClz (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateEor (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateLdmStm (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateLdr (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateLdrd (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateMla (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateMls (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateMov (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateMovt (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateMovw (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateMul (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateNop (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateOrr (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateRev (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateSbc (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateShifts (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateStr (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateSub (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateUmlal (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateUmull (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateUxtah (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateUxtb (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateUxtb16 (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
void translateUxth (cs_insn *i, cs_arm *ai, llvm::IRBuilder<> &irb)
 
- Protected Member Functions inherited from retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >
llvm::Value * generateTypeConversion (llvm::IRBuilder<> &irb, llvm::Value *from, llvm::Type *to, eOpConv ct)
 
llvm::Type * _checkTypeConversion (llvm::IRBuilder<> &irb, llvm::Type *to, eOpConv ct)
 
virtual void initialize ()
 
virtual void openHandle ()
 
virtual void configureHandle ()
 
virtual void closeHandle ()
 
virtual void generateEnvironment ()
 
virtual void generateSpecialAsm2LlvmMapGlobal ()
 
virtual llvm::StoreInst * generateSpecialAsm2LlvmInstr (llvm::IRBuilder<> &irb, cs_insn *i)
 
virtual void generateCallFunction ()
 
virtual llvm::CallInst * generateCallFunctionCall (llvm::IRBuilder<> &irb, llvm::Value *t)
 
virtual llvm::CallInst * generateCondCallFunctionCall (llvm::IRBuilder<> &irb, llvm::Value *cond, llvm::Value *t)
 
virtual void generateReturnFunction ()
 
virtual llvm::CallInst * generateReturnFunctionCall (llvm::IRBuilder<> &irb, llvm::Value *t)
 
virtual llvm::CallInst * generateCondReturnFunctionCall (llvm::IRBuilder<> &irb, llvm::Value *cond, llvm::Value *t)
 
virtual void generateBranchFunction ()
 
virtual llvm::CallInst * generateBranchFunctionCall (llvm::IRBuilder<> &irb, llvm::Value *t)
 
virtual void generateCondBranchFunction ()
 
virtual llvm::CallInst * generateCondBranchFunctionCall (llvm::IRBuilder<> &irb, llvm::Value *cond, llvm::Value *t)
 
virtual llvm::GlobalVariable * createRegister (uint32_t r, llvm::GlobalValue::LinkageTypes lt=llvm::GlobalValue::LinkageTypes::InternalLinkage, llvm::Constant *initializer=nullptr)
 
virtual llvm::Value * loadRegister (uint32_t r, llvm::IRBuilder<> &irb, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::THROW)=0
 
llvm::Value * loadOp (cs_arm *ci, llvm::IRBuilder<> &irb, std::size_t idx, llvm::Type *loadType=nullptr, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::NOTHING)
 
virtual llvm::Instruction * storeRegister (uint32_t r, llvm::Value *val, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::SEXT_TRUNC_OR_BITCAST)=0
 
virtual llvm::Instruction * storeOp (cs_arm_op &op, llvm::Value *val, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::SEXT_TRUNC_OR_BITCAST)=0
 
std::vector< llvm::Value * > _loadOps (cs_arm *ci, llvm::IRBuilder<> &irb, std::size_t opCnt, bool strictCheck=true, llvm::Type *loadType=nullptr, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::NOTHING)
 
std::vector< llvm::Value * > _loadOpsUniversal (cs_arm *ci, llvm::IRBuilder<> &irb, std::size_t opCnt, bool strictCheck=true, eOpConv ict=eOpConv::SEXT_TRUNC_OR_BITCAST, eOpConv fct=eOpConv::FPCAST_OR_BITCAST)
 
llvm::Value * loadOpUnary (cs_arm *ci, llvm::IRBuilder<> &irb, llvm::Type *dstType=nullptr, llvm::Type *loadType=nullptr, eOpConv ct=eOpConv::THROW)
 
std::pair< llvm::Value *, llvm::Value * > loadOpBinary (cs_arm *ci, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::NOTHING)
 
std::pair< llvm::Value *, llvm::Value * > loadOpBinary (cs_arm *ci, llvm::IRBuilder<> &irb, eOpConv ict, eOpConv fct)
 
std::pair< llvm::Value *, llvm::Value * > loadOpBinary (cs_arm *ci, llvm::IRBuilder<> &irb, llvm::Type *loadType, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::NOTHING)
 
llvm::Value * loadOpBinaryOp0 (cs_arm *ci, llvm::IRBuilder<> &irb, llvm::Type *ty=nullptr)
 
llvm::Value * loadOpBinaryOp1 (cs_arm *ci, llvm::IRBuilder<> &irb, llvm::Type *ty=nullptr)
 
std::tuple< llvm::Value *, llvm::Value *, llvm::Value * > loadOpTernary (cs_arm *ci, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::NOTHING)
 
std::tuple< llvm::Value *, llvm::Value *, llvm::Value * > loadOpTernary (cs_arm *ci, llvm::IRBuilder<> &irb, eOpConv ict, eOpConv fct)
 
std::tuple< llvm::Value *, llvm::Value *, llvm::Value * > loadOpTernary (cs_arm *ci, llvm::IRBuilder<> &irb, llvm::Type *loadType, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::NOTHING)
 
std::pair< llvm::Value *, llvm::Value * > loadOpBinaryOrTernaryOp1Op2 (cs_arm *ai, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::NOTHING)
 
std::pair< llvm::Value *, llvm::Value * > loadOpBinaryOrTernaryOp1Op2 (cs_arm *ai, llvm::IRBuilder<> &irb, eOpConv ict, eOpConv fct)
 
std::tuple< llvm::Value *, llvm::Value *, llvm::Value * > loadOpQuaternaryOp1Op2Op3 (cs_arm *ai, llvm::IRBuilder<> &irb)
 
llvm::Value * generateCarryAdd (llvm::Value *add, llvm::Value *op0, llvm::IRBuilder<> &irb)
 
llvm::Value * generateCarryAddC (llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb, llvm::Value *cf=nullptr)
 
llvm::Value * generateCarryAddInt4 (llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb)
 
llvm::Value * generateCarryAddCInt4 (llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb, llvm::Value *cf=nullptr)
 
llvm::Value * generateOverflowAdd (llvm::Value *add, llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb)
 
llvm::Value * generateOverflowAddC (llvm::Value *add, llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb, llvm::Value *cf=nullptr)
 
llvm::Value * generateOverflowSub (llvm::Value *sub, llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb)
 
llvm::Value * generateOverflowSubC (llvm::Value *sub, llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb, llvm::Value *cf=nullptr)
 
llvm::Value * generateBorrowSub (llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb)
 
llvm::Value * generateBorrowSubC (llvm::Value *sub, llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb, llvm::Value *cf=nullptr)
 
llvm::Value * generateBorrowSubInt4 (llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb)
 
llvm::Value * generateBorrowSubCInt4 (llvm::Value *op0, llvm::Value *op1, llvm::IRBuilder<> &irb, llvm::Value *cf=nullptr)
 
llvm::IntegerType * getDefaultType ()
 
llvm::Value * getThisInsnAddress (cs_insn *i)
 
llvm::Value * getNextInsnAddress (cs_insn *i)
 
llvm::BranchInst * getCondBranchForInsnInIfThen (llvm::Instruction *i) const
 
std::string getPseudoAsmFunctionName (cs_insn *insn)
 
llvm::Function * getPseudoAsmFunction (cs_insn *insn, llvm::FunctionType *type, const std::string &name="")
 
llvm::Function * getPseudoAsmFunction (cs_insn *insn, llvm::Type *retType, llvm::ArrayRef< llvm::Type * > params, const std::string &name="")
 
void translatePseudoAsmOp0Fnc (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmFncOp0 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp0 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmFncOp0Op1 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp1 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp0Op1 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmFncOp0Op1Op2 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp1Op2 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp0Op1Op2 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmFncOp0Op1Op2Op3 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp1Op2Op3 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0FncOp0Op1Op2Op3 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void translatePseudoAsmOp0Op1FncOp0Op1Op2Op3 (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
virtual uint8_t getOperandAccess (cs_arm_op &op)
 
virtual void translatePseudoAsmGeneric (cs_insn *i, cs_arm *ci, llvm::IRBuilder<> &irb)
 
void throwUnexpectedOperands (cs_insn *i, const std::string comment="")
 
void throwUnhandledInstructions (cs_insn *i, const std::string comment="")
 

Static Protected Attributes

static std::map< std::size_t, void(Capstone2LlvmIrTranslatorArm_impl::*)(cs_insn *i, cs_arm *, llvm::IRBuilder<> &)> _i2fm
 

Additional Inherited Members

- Static Public Member Functions inherited from retdec::capstone2llvmir::Capstone2LlvmIrTranslator
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateArch (cs_arch a, llvm::Module *m, cs_mode basic=CS_MODE_LITTLE_ENDIAN, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateArm (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateThumb (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateArm64 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateMips32 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateMips64 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateMips3 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateMips32R6 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateX86_16 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateX86_32 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateX86_64 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreatePpc32 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreatePpc64 (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreatePpcQpx (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateSparc (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateSysz (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
static std::unique_ptr< Capstone2LlvmIrTranslatorcreateXcore (llvm::Module *m, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
 
- Protected Types inherited from retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >
enum class  eOpConv
 
- Protected Attributes inherited from retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >
csh _handle
 
cs_arch _arch
 
cs_mode _basicMode
 
cs_mode _extraMode
 
cs_mode _origBasicMode
 
llvm::Module * _module
 
llvm::GlobalVariable * _asm2llvmGv
 
llvm::Function * _callFunction
 
llvm::Function * _returnFunction
 
llvm::Function * _branchFunction
 
llvm::Function * _condBranchFunction
 
llvm::GlobalValue::LinkageTypes _regLt
 
std::map< std::pair< std::string, llvm::FunctionType * >, llvm::Function * > _insn2asmFunctions
 (fnc_name, fnc_type) -> fnc More...
 
std::set< llvm::Function * > _asmFunctions
 
std::map< uint32_t, std::string > _reg2name
 
std::map< uint32_t, llvm::Type * > _reg2type
 
std::map< llvm::GlobalVariable *, uint32_t > _llvm2CapstoneRegs
 
std::map< uint32_t, llvm::GlobalVariable * > _capstone2LlvmRegs
 
llvm::CallInst * _branchGenerated
 
bool _inCondition
 
llvm::Value * op0
 
llvm::Value * op1
 
llvm::Value * op2
 
llvm::Value * op3
 
cs_insn * _insn
 Capstone instruction being currently translated. More...
 
std::set< unsigned int > _callInsnIds
 
std::set< unsigned int > _returnInsnIds
 
std::set< unsigned int > _branchInsnIds
 
std::set< unsigned int > _condBranchInsnIds
 
std::set< unsigned int > _controlFlowInsnIds
 
bool _ignoreUnexpectedOperands
 
bool _ignoreUnhandledInstructions
 
bool _generatePseudoAsmFunctions
 

Constructor & Destructor Documentation

◆ Capstone2LlvmIrTranslatorArm_impl()

retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::Capstone2LlvmIrTranslatorArm_impl ( llvm::Module *  m,
cs_mode  basic = CS_MODE_ARM,
cs_mode  extra = CS_MODE_LITTLE_ENDIAN 
)

Member Function Documentation

◆ generateDataLayout()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateDataLayout ( )
overrideprotectedvirtual

Generate LLVM data layout into the module. This is architecture and mode specific and must be implemented in concrete classes.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ generateEnvironmentArchSpecific()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateEnvironmentArchSpecific ( )
overrideprotectedvirtual

Generate architecture specific environment on top of common environment generated by generateEnvironment().

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ generateInsnConditionCode()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateInsnConditionCode ( llvm::IRBuilder<> &  irb,
cs_arm *  ai 
)
protected

◆ generateOperandShift()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateOperandShift ( llvm::IRBuilder<> &  irb,
cs_arm_op &  op,
llvm::Value *  val 
)
protected

◆ generateRegisters()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateRegisters ( )
overrideprotectedvirtual

Generate LLVM global variables for registers. This is architecture and mode specific and must be implemented in concrete classes.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ generateShiftAsr()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateShiftAsr ( llvm::IRBuilder<> &  irb,
llvm::Value *  val,
llvm::Value *  n 
)
protected

◆ generateShiftLsl()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateShiftLsl ( llvm::IRBuilder<> &  irb,
llvm::Value *  val,
llvm::Value *  n 
)
protected

◆ generateShiftLsr()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateShiftLsr ( llvm::IRBuilder<> &  irb,
llvm::Value *  val,
llvm::Value *  n 
)
protected

◆ generateShiftRor()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateShiftRor ( llvm::IRBuilder<> &  irb,
llvm::Value *  val,
llvm::Value *  n 
)
protected

◆ generateShiftRrx()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::generateShiftRrx ( llvm::IRBuilder<> &  irb,
llvm::Value *  val,
llvm::Value *  n 
)
protected

◆ getArchByteSize()

uint32_t retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::getArchByteSize ( )
overridevirtual
Returns
Architecture byte size according to the currently set basic mode.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator.

◆ getCarryRegister()

uint32_t retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::getCarryRegister ( )
overrideprotectedvirtual

◆ getCurrentPc()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::getCurrentPc ( cs_insn *  i)
protected

During execution, PC does not contain the address of the currently executing instruction. The address of the currently executing instruction is typically PC-8 for ARM, or PC-4 for Thumb.

In Thumb state:

  • For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.
  • For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.

ARM: current = PC - 8 => PC = current + 8 = current + 2*4 = current + 2*insn_size

THUMB: current = PC - 4 => PC = current + 4 = current + 2*2 = current + 2*insn_size

◆ getOperandAccess()

uint8_t retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::getOperandAccess ( cs_arm_op &  op)
overrideprotectedvirtual

◆ initializeArchSpecific()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::initializeArchSpecific ( )
overrideprotectedvirtual

Do architecture and mode specific initialization on top of common initialization done by initialize();

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ initializePseudoCallInstructionIDs()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::initializePseudoCallInstructionIDs ( )
overrideprotectedvirtual

If possible, initialize _callInsnIds, _returnInsnIds, _branchInsnIds, _condBranchInsnIds, _condBranchInsnIds sets.

For some architectures, it is not possible to initialize all the instructions that may generate control flow change. E.g. Any kind of ARM instruction that writes to PC is changing control flow.

This is not ideal, because each time some instruction that generates one of these is added, or removed, its ID must also be manualy added, or removed, here. This could be easily forgotten. Right now, I do not know how to solve this better (i.e. automatic update).

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ initializeRegNameMap()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::initializeRegNameMap ( )
overrideprotectedvirtual

Initialize _reg2name. See comment for _reg2name to know what must be initialized, and what may or may not be initialized.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ initializeRegTypeMap()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::initializeRegTypeMap ( )
overrideprotectedvirtual

Initialize _reg2type. See comment for _reg2type to know what must be initialized, and what may or may not be initialized.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ isAllowedBasicMode()

bool retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::isAllowedBasicMode ( cs_mode  m)
overridevirtual

Check if mode m is an allowed basic mode for the translator. This must be implemented in concrete classes, since it is architecture and translator specific.

Returns
True if mode is allowed, false otherwise.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator.

◆ isAllowedExtraMode()

bool retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::isAllowedExtraMode ( cs_mode  m)
overridevirtual

Check if mode m is an allowed extra mode for the translator. This must be implemented in concrete classes, since it is architecture and translator specific.

Returns
True if mode is allowed, false otherwise.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator.

◆ isOperandRegister()

bool retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::isOperandRegister ( cs_arm_op &  op)
overrideprotectedvirtual

◆ loadOp()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::loadOp ( cs_arm_op &  op,
llvm::IRBuilder<> &  irb,
llvm::Type *  ty = nullptr,
bool  lea = false 
)
overrideprotectedvirtual

◆ loadRegister()

llvm::Value * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::loadRegister ( uint32_t  r,
llvm::IRBuilder<> &  irb,
llvm::Type *  dstType = nullptr,
eOpConv  ct = eOpConv::THROW 
)
overrideprotectedvirtual

◆ storeOp()

llvm::Instruction * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::storeOp ( cs_arm_op &  op,
llvm::Value *  val,
llvm::IRBuilder<> &  irb,
eOpConv  ct = eOpConv::SEXT_TRUNC_OR_BITCAST 
)
overrideprotectedvirtual

◆ storeRegister()

llvm::Instruction * retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::storeRegister ( uint32_t  r,
llvm::Value *  val,
llvm::IRBuilder<> &  irb,
eOpConv  ct = eOpConv::SEXT_TRUNC_OR_BITCAST 
)
overrideprotectedvirtual

◆ sysregNumberTranslation()

uint32_t retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::sysregNumberTranslation ( uint32_t  r)
protected

We cannot use some sysreg ID numbers -> translate them to other ID numbers. See comment for arm_sysreg_extension for more details.

◆ translateAdc()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateAdc ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_ADC TODO: Castone sets update_flags==true even when "adc", not "adcs". Check once more and report as bug.

◆ translateAdd()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateAdd ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_ADD, ARM_INS_CMN (ADDS but result is discarded)

◆ translateAnd()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateAnd ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_AND, ARM_INS_BIC, ARM_INS_TST (ANDS but result is discarded)

◆ translateB()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateB ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_B, ARM_INS_BX (exchange instruction)

◆ translateBl()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateBl ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_BL, ARM_INS_BLX (exchange instruction)

◆ translateCbnz()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateCbnz ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_CBNZ

◆ translateCbz()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateCbz ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_CBZ

◆ translateClz()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateClz ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_CLZ

◆ translateEor()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateEor ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_EOR, ARM_INS_TEQ (EORS but result is discarded)

◆ translateInstruction()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateInstruction ( cs_insn *  i,
llvm::IRBuilder<> &  irb 
)
overrideprotectedvirtual

Translate single Capstone instruction.

Implements retdec::capstone2llvmir::Capstone2LlvmIrTranslator_impl< cs_arm, cs_arm_op >.

◆ translateLdmStm()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateLdmStm ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_LDM = IA (increment after) = LDMFD (synonym, IDA) ARM_INS_LDMIB = IB (increment before) (ARM only) ARM_INS_LDMDA = DA (decrement after) (ARM only) ARM_INS_LDMDB = DB (decrement before) ARM_INS_POP = LDMIA sp! reglist (writeback to SP, increment after)

ARM_INS_STM = IA (increment after) ARM_INS_STMIB = IB (increment before) (ARM only) ARM_INS_STMDA = DA (decrement after) (ARM only) ARM_INS_STMDB = DB (decrement before) = STMFD (synonym, IDA) ARM_INS_PUSH = STMDB sp!, reglist (writeback to SP, decrement before)

ARM_INS_PUSH (ARM_INS_STMDB): Registers are stored on the stack in numerical order, with the lowest numbered register at the lowest address. TODO: Is this also true for ARM_INS_STMDA? Are increment variants ok?

TODO: If PC is loaded (store to PC -> branch), then we might generate uncond branch in the middle of the instruction -> before all of it is executed. We should remember such branch and generate it last, because in CPU, all the instruction is executed.

◆ translateLdr()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateLdr ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_LDR (word) = ARM_INS_LDRT (unprivileged) ARM_INS_LDRB (unsigned byte) = ARM_INS_LDRBT (unprivileged) ARM_INS_LDRSB (signed byte) = ARM_INS_LDRSBT (unprivileged) ARM_INS_LDRH (unsigned half word) = ARM_INS_LDRHT (unprivileged) ARM_INS_LDRSH (signed half word) = ARM_INS_LDRSHT (unprivileged)

ARM_INS_LDREX, ARM_INS_LDREXB, ARM_INS_LDREXH = Exclusive: Conditional load, conditions check physical address atributes (e.g. TLB). We are not able to check those here. Right now, we just ignore it and generate ordinary loads, but we might generate ASM pseudo insn fnc call.

LDR R0, [R4, #4] ; simple offset: R0 = *(int*)(R4+4); R4 unchanged LDR R0, [R4, #4]! ; pre-indexed : R0 = *(int*)(R4+4); R4 = R4+4 LDR R0, [R4], #4 ; post-indexed : R0 = *(int*)(R4+0); R4 = R4+4

TODO: "20 f5 bc e5" = "ldr pc, [ip, #0x520]!" -> write to PC -> branch, writeback is generated after the branch call -> problem here, and probably everywhere where writeback is generated. In these cases, branch generated for PC write should be the last instruction.

◆ translateLdrd()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateLdrd ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_LDRD (double word) ARM_INS_LDREXD (exclusive, see translateLdr())

◆ translateMla()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateMla ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_MLA

◆ translateMls()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateMls ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_MLS

◆ translateMov()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateMov ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_MOV, ARM_INS_MVN,

◆ translateMovt()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateMovt ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_MOVT

◆ translateMovw()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateMovw ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_MOVW

◆ translateMul()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateMul ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_MUL

◆ translateNop()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateNop ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_NOP

◆ translateOrr()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateOrr ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_ORR

◆ translateRev()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateRev ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_REV

◆ translateSbc()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateSbc ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_SBC, ARM_INS_RSC TODO: The same flag-update problem as with ARM_INS_ADC.

◆ translateShifts()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateShifts ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

Preferred synonyms for MOV instructions with shifted register operands: ARM_INS_LSL, ARM_INS_LSR, ARM_INS_ROR, ARM_INS_RRX, ARM_INS_ASR

TODO: Report Capstone bug:

  • When shift is imm, it is ok – imm is part of the operand to be shifted. e.g. lsl r0, r1, #4 = 2 operands, 4 and LSL part of r1 operand.
  • When shift is reg, it is NOT ok – reg is NOT a part of the operand to be shifted, even though it could be. e.g. lsl r0, r1, r2 = 3 operands, r1 have ARM_SFT_INVALID, r2 separate op. It should be 2 operands, r1 with ARM_SFT_LSL_REG, r2 in r1 op as shift val.
  • On THUMB, not even imm is ok, it creates 3th operand as well.

◆ translateStr()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateStr ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_STR (word) == ARM_INS_STRT (unprivileged) ARM_INS_STRB (byte) == ARM_INS_STRBT (unprivileged) ARM_INS_STRH (half word) == ARM_INS_STRHT (unprivileged) ARM_INS_STRD (double word)

ARM_INS_STREX, ARM_INS_STREXB, ARM_INS_STREXH, ARM_INS_STREXD = Exclusive: Conditional store, conditions check physical address atributes (e.g. TLB). We are not able to check those here. Right now, we just ignore it and generate ordinary stores, but we might generate ASM pseudo insn fnc call. TODO: One more operand - first operand is set to dst reg for returned status -> Translation disabled, this will need more work to work.

STR R0, [R4, #4] ; simple offset: *(int*)(R4+4) = R0; R4 unchanged STR R0, [R4, #4]! ; pre-indexed : *(int*)(R4+4) = R0; R4 = R4+4 STR R0, [R4], #4 ; post-indexed : *(int*)(R4+0) = R0; R4 = R4+4

◆ translateSub()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateSub ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_SUB, ARM_INS_RSB, ARM_INS_CMP (SUBS but result is discarded)

◆ translateUmlal()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateUmlal ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_UMLAL, ARM_INS_SMLAL

◆ translateUmull()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateUmull ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_UMULL, ARM_INS_SMULL

◆ translateUxtah()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateUxtah ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_UXTAH

◆ translateUxtb()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateUxtb ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_UXTB

◆ translateUxtb16()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateUxtb16 ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_UXTB16

◆ translateUxth()

void retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::translateUxth ( cs_insn *  i,
cs_arm *  ai,
llvm::IRBuilder<> &  irb 
)
protected

ARM_INS_UXTH

Member Data Documentation

◆ _i2fm

std::map< std::size_t, void(Capstone2LlvmIrTranslatorArm_impl::*)(cs_insn *i, cs_arm *, llvm::IRBuilder<> &)> retdec::capstone2llvmir::Capstone2LlvmIrTranslatorArm_impl::_i2fm
staticprotected

The documentation for this class was generated from the following files: