retdec
arm64_impl.h
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1 
7 #ifndef CAPSTONE2LLVMIR_ARM64_ARM64_IMPL_H
8 #define CAPSTONE2LLVMIR_ARM64_ARM64_IMPL_H
9 
12 
13 namespace retdec {
14 namespace capstone2llvmir {
15 
17  public Capstone2LlvmIrTranslator_impl<cs_arm64, cs_arm64_op>,
19 {
20  public:
22  llvm::Module* m,
23  cs_mode basic = CS_MODE_ARM,
24  cs_mode extra = CS_MODE_LITTLE_ENDIAN);
25 //
26 //==============================================================================
27 // Mode query & modification methods - from Capstone2LlvmIrTranslator.
28 //==============================================================================
29 //
30  public:
31  virtual bool isAllowedBasicMode(cs_mode m) override;
32  virtual bool isAllowedExtraMode(cs_mode m) override;
33  virtual uint32_t getArchByteSize() override;
34 
35 //
36 //==============================================================================
37 // Arm64 specialization methods - from Capstone2LlvmIrTranslatorArm64
38 //==============================================================================
39 //
40  public:
41 
42  virtual uint32_t getParentRegister(uint32_t r) const override;
43 //
44 //==============================================================================
45 // Pure virtual methods from Capstone2LlvmIrTranslator_impl
46 //==============================================================================
47 //
48  protected:
49  virtual void initializeArchSpecific() override;
50  virtual void initializeRegNameMap() override;
51  virtual void initializeRegTypeMap() override;
52  virtual void initializePseudoCallInstructionIDs() override;
53  virtual void generateEnvironmentArchSpecific() override;
54  virtual void generateDataLayout() override;
55  virtual void generateRegisters() override;
56  virtual uint32_t getCarryRegister() override;
57 
58  virtual void translateInstruction(
59  cs_insn* i,
60  llvm::IRBuilder<>& irb) override;
61 //
62 //==============================================================================
63 // ARM64-specific methods.
64 //==============================================================================
65 //
66  protected:
67  llvm::Value* getCurrentPc(cs_insn* i);
68 
70  const std::vector<arm64_reg>& rs,
71  arm64_reg other);
72 
74 
75  llvm::Value* extractVectorValue(
76  llvm::IRBuilder<>& irb,
77  cs_arm64_op& op,
78  llvm::Value* val);
79 
80  llvm::Value* generateOperandExtension(
81  llvm::IRBuilder<>& irb,
82  arm64_extender ext,
83  llvm::Value* val,
84  llvm::Type* destType = nullptr);
85 
86  llvm::Value* generateOperandShift(
87  llvm::IRBuilder<>& irb,
88  cs_arm64_op& op,
89  llvm::Value* val,
90  bool updateFlags = false);
91  llvm::Value* generateShiftAsr(
92  llvm::IRBuilder<>& irb,
93  llvm::Value* val,
94  llvm::Value* n,
95  bool updateFlags = false);
96  llvm::Value* generateShiftLsl(
97  llvm::IRBuilder<>& irb,
98  llvm::Value* val,
99  llvm::Value* n,
100  bool updateFlags = false);
101  llvm::Value* generateShiftLsr(
102  llvm::IRBuilder<>& irb,
103  llvm::Value* val,
104  llvm::Value* n,
105  bool updateFlags = false);
106  llvm::Value* generateShiftRor(
107  llvm::IRBuilder<>& irb,
108  llvm::Value* val,
109  llvm::Value* n,
110  bool updateFlags = false);
111  llvm::Value* generateShiftMsl(
112  llvm::IRBuilder<>& irb,
113  llvm::Value* val,
114  llvm::Value* n,
115  bool updateFlags = false);
116 
117  llvm::Value* generateInsnConditionCode(
118  llvm::IRBuilder<>& irb,
119  cs_arm64* ai);
120 
121  llvm::Value* generateGetOperandMemAddr(
122  cs_arm64_op& op,
123  llvm::IRBuilder<>& irb);
124 
125  virtual llvm::Value* loadRegister(
126  uint32_t r,
127  llvm::IRBuilder<>& irb,
128  llvm::Type* dstType = nullptr,
129  eOpConv ct = eOpConv::THROW) override;
130  virtual llvm::Value* loadOp(
131  cs_arm64_op& op,
132  llvm::IRBuilder<>& irb,
133  llvm::Type* ty = nullptr,
134  bool lea = false) override;
135 
136  virtual llvm::Instruction* storeRegister(
137  uint32_t r,
138  llvm::Value* val,
139  llvm::IRBuilder<>& irb,
140  eOpConv ct = eOpConv::ZEXT_TRUNC_OR_BITCAST) override;
141  virtual llvm::Instruction* storeOp(
142  cs_arm64_op& op,
143  llvm::Value* val,
144  llvm::IRBuilder<>& irb,
145  eOpConv ct = eOpConv::ZEXT_TRUNC_OR_BITCAST) override;
146 
152  void generatePseudoInstruction(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
153 
154  using _translator_fnc = void (Capstone2LlvmIrTranslatorArm64_impl::*)(cs_insn* i, cs_arm64*, llvm::IRBuilder<>&);
155  bool ifVectorGeneratePseudo(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb, _translator_fnc = nullptr);
156  llvm::Value* generateFPBitCastToIntegerType(llvm::IRBuilder<>& irb, llvm::Value* val) const;
157  llvm::Value* generateIntBitCastToFP(llvm::IRBuilder<>& irb, llvm::Value* val) const;
158 //
159 //==============================================================================
160 // Helper methods.
161 //==============================================================================
162 //
163  protected:
164 
165  bool isCondIns(cs_arm64 * i) const;
166 
172  bool isFPRegister(cs_arm64_op& op, bool onlySupported = true) const;
173 
179  bool isVectorRegister(cs_arm64_op& op) const;
180 
181  virtual bool isOperandRegister(cs_arm64_op& op) override;
182  virtual uint8_t getOperandAccess(cs_arm64_op& op) override;
183 //
184 //==============================================================================
185 // ARM64 implementation data.
186 //==============================================================================
187 //
188  protected:
189 
191  std::map<uint32_t, uint32_t> _reg2parentMap;
192 
193  static std::map<
194  std::size_t,
196 //
197 //==============================================================================
198 // ARM64 instruction translation methods.
199 //==============================================================================
200 //
201  protected:
202  void translateAdc(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
203  void translateAdd(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
204  void translateAnd(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
205  void translateCondOp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
206  void translateCondSelOp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
207  void translateCondCompare(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
208  void translateClz(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
209  void translateShifts(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
210  void translateSub(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
211  void translateNeg(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
212  void translateNgc(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
213  void translateSbc(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
214  void translateMov(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
215  void translateMovk(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
216  void translateStr(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
217  void translateStp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
218  void translateLdr(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
219  void translateLdp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
220  void translateAdr(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
221  void translateB(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
222  void translateBl(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
223  void translateBr(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
224  void translateCbnz(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
225  void translateCsel(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
226  void translateCset(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
227  void translateDiv(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
228  void translateEor(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
229  void translateExtensions(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
230  void translateExtr(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
231  void translateOrr(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
232  void translateMul(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
233  void translateMulOpl(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
234  void translateMull(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
235  void translateMulh(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
236  void translateNop(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
237  void translateTbnz(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
238  void translateRet(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
239  void translateRev(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
240 
241  // FP - instructions
242  void translateFAdd(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
243  void translateFCmp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
244  void translateFCCmp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
245  void translateFCsel(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
246  void translateFCvt(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
247  void translateFCvtf(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
248  void translateFCvtz(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
249  void translateFDiv(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
250  void translateFMadd(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
251  void translateFMinMax(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
252  void translateFMinMaxNum(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
253  void translateFMsub(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
254  void translateFMov(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
255  void translateMovi(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
256  void translateFMul(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
257  void translateFSub(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
258  void translateFUnaryOp(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
259 };
260 
261 } // namespace capstone2llvmir
262 } // namespace retdec
263 
264 #endif /* CAPSTONE2LLVMIR_ARM64_ARM64_IMPL_H */
ARM64 specialization of translator's abstract public interface.
Common private implementation for translators converting bytes to LLVM IR.
void translateNop(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1346
void translateExtr(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2194
void translateShifts(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1804
virtual bool isOperandRegister(cs_arm64_op &op) override
Definition: arm64.cpp:1019
llvm::Value * generateShiftMsl(llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n, bool updateFlags=false)
Definition: arm64.cpp:600
llvm::Value * getCurrentPc(cs_insn *i)
Definition: arm64.cpp:363
void translateDiv(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2235
void translateFMsub(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2952
void translateLdp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1671
void translateRev(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2540
virtual uint32_t getCarryRegister() override
Definition: arm64.cpp:317
virtual uint8_t getOperandAccess(cs_arm64_op &op) override
Definition: arm64.cpp:1051
virtual uint32_t getArchByteSize() override
Definition: arm64.cpp:44
virtual void initializeArchSpecific() override
Definition: arm64_init.cpp:21
llvm::Value * generateShiftLsr(llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n, bool updateFlags=false)
Definition: arm64.cpp:559
void translateClz(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1894
void translateBl(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1882
void translateFCvtz(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2752
void translateFMinMaxNum(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2846
void translateLdr(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1554
llvm::Value * generateIntBitCastToFP(llvm::IRBuilder<> &irb, llvm::Value *val) const
Definition: arm64.cpp:1061
void translateCondSelOp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2042
void translateMulOpl(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2375
bool isFPRegister(cs_arm64_op &op, bool onlySupported=true) const
Check if register is FP type.
Definition: arm64.cpp:1024
void translateOrr(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2216
llvm::Value * generateFPBitCastToIntegerType(llvm::IRBuilder<> &irb, llvm::Value *val) const
Definition: arm64.cpp:1079
void translateFUnaryOp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2991
bool isVectorRegister(cs_arm64_op &op) const
Check if register is Vector type. This is true for all ARM64_REG_V* registers.
Definition: arm64.cpp:1046
virtual llvm::Instruction * storeOp(cs_arm64_op &op, llvm::Value *val, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::ZEXT_TRUNC_OR_BITCAST) override
Definition: arm64.cpp:856
void translateFCvtf(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2730
llvm::Value * generateShiftLsl(llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n, bool updateFlags=false)
Definition: arm64.cpp:541
void translateFSub(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2972
llvm::Value * generateGetOperandMemAddr(cs_arm64_op &op, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:635
void translateCsel(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1987
void translateMull(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2328
void translateFAdd(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2573
void translateEor(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2111
void translateFCCmp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2592
std::map< uint32_t, uint32_t > _reg2parentMap
Mapping from register to its parent register.
Definition: arm64_impl.h:191
void(Capstone2LlvmIrTranslatorArm64_impl::*)(cs_insn *i, cs_arm64 *, llvm::IRBuilder<> &) _translator_fnc
Definition: arm64_impl.h:154
void translateExtensions(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2131
virtual void generateRegisters() override
Definition: arm64.cpp:66
void translateAdc(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1158
void translateSub(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1217
void translateFCmp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2654
virtual uint32_t getParentRegister(uint32_t r) const override
Definition: arm64.cpp:346
void translateMovi(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2906
virtual bool isAllowedBasicMode(cs_mode m) override
Definition: arm64.cpp:34
void translateSbc(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1284
void translateCondCompare(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1936
bool isCondIns(cs_arm64 *i) const
Definition: arm64.cpp:1056
void translateNeg(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1252
void translateAdd(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1183
void translateCset(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2081
virtual void generateDataLayout() override
Definition: arm64.cpp:60
virtual void translateInstruction(cs_insn *i, llvm::IRBuilder<> &irb) override
Definition: arm64.cpp:322
llvm::Value * generateOperandExtension(llvm::IRBuilder<> &irb, arm64_extender ext, llvm::Value *val, llvm::Type *destType=nullptr)
Definition: arm64.cpp:406
void translateFCvt(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2719
void translateFCsel(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2703
void initializeRegistersParentMapToOther(const std::vector< arm64_reg > &rs, arm64_reg other)
Definition: arm64_init.cpp:1549
llvm::Value * generateOperandShift(llvm::IRBuilder<> &irb, cs_arm64_op &op, llvm::Value *val, bool updateFlags=false)
Definition: arm64.cpp:471
void translateStp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1499
virtual void initializeRegNameMap() override
Definition: arm64_init.cpp:26
bool ifVectorGeneratePseudo(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb, _translator_fnc=nullptr)
Definition: arm64.cpp:1121
virtual bool isAllowedExtraMode(cs_mode m) override
Definition: arm64.cpp:39
void translateNgc(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1315
void translateCbnz(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1912
void translateMulh(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2283
virtual void initializeRegTypeMap() override
Definition: arm64_init.cpp:619
void translateCondOp(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2002
llvm::Value * extractVectorValue(llvm::IRBuilder<> &irb, cs_arm64_op &op, llvm::Value *val)
Definition: arm64.cpp:370
void translateFMadd(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2794
virtual void generateEnvironmentArchSpecific() override
Definition: arm64.cpp:55
llvm::Value * generateInsnConditionCode(llvm::IRBuilder<> &irb, cs_arm64 *ai)
Definition: arm64.cpp:900
void translateMov(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1354
void translateStr(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1410
static std::map< std::size_t, _translator_fnc > _i2fm
Definition: arm64_impl.h:195
void translateFDiv(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2775
void translateRet(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2520
virtual llvm::Value * loadRegister(uint32_t r, llvm::IRBuilder<> &irb, llvm::Type *dstType=nullptr, eOpConv ct=eOpConv::THROW) override
Definition: arm64.cpp:682
void translateFMov(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2879
virtual llvm::Instruction * storeRegister(uint32_t r, llvm::Value *val, llvm::IRBuilder<> &irb, eOpConv ct=eOpConv::ZEXT_TRUNC_OR_BITCAST) override
Definition: arm64.cpp:794
void initializeRegistersParentMap()
Definition: arm64_init.cpp:1559
virtual void initializePseudoCallInstructionIDs() override
Definition: arm64_init.cpp:1515
void translateBr(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1846
void translateAnd(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1771
Capstone2LlvmIrTranslatorArm64_impl(llvm::Module *m, cs_mode basic=CS_MODE_ARM, cs_mode extra=CS_MODE_LITTLE_ENDIAN)
Definition: arm64.cpp:18
void translateMovk(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1375
llvm::Value * generateShiftRor(llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n, bool updateFlags=false)
Definition: arm64.cpp:577
llvm::Value * generateShiftAsr(llvm::IRBuilder<> &irb, llvm::Value *val, llvm::Value *n, bool updateFlags=false)
Definition: arm64.cpp:524
void translateFMul(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2929
void translateTbnz(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2490
void translateAdr(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1744
void translateFMinMax(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2814
void translateMul(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:2455
void translateB(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
Definition: arm64.cpp:1863
virtual llvm::Value * loadOp(cs_arm64_op &op, llvm::IRBuilder<> &irb, llvm::Type *ty=nullptr, bool lea=false) override
Definition: arm64.cpp:737
void generatePseudoInstruction(cs_insn *i, cs_arm64 *ai, llvm::IRBuilder<> &irb)
This functions will generate psuedo asm translation. Instructions that are not implemented fall back ...
Definition: arm64.cpp:1101
Definition: capstone2llvmir_impl.h:32
Definition: archive_wrapper.h:19