Function core::arch::mips::__msa_srl_b

source ·
pub unsafe fn __msa_srl_b(a: v16i8, b: v16i8) -> v16i8
🔬This is a nightly-only experimental API. (stdsimd #48556)
Available on (MIPS or MIPS-64) and target feature msa and MIPS only.
Expand description

Vector Shift Right Logical

The elements in vector a (sixteen signed 8-bit integer numbers) are shifted right logical by the number of bits the elements in vector b (sixteen signed 8-bit integer numbers) specify modulo the size of the element in bits.The result is written to vector (sixteen signed 8-bit integer numbers).