Function core::arch::mips64::__msa_and_v

source ·
pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8
🔬This is a nightly-only experimental API. (stdsimd #48556)
Available on (MIPS or MIPS-64) and target feature msa and MIPS-64 only.
Expand description

Vector Logical And

Each bit of vector a (sixteen unsigned 8-bit integer numbers) is combined with the corresponding bit of vector b (sixteen unsigned 8-bit integer numbers) in a bitwise logical AND operation. The result is written to vector (sixteen unsigned 8-bit integer numbers).