Function core::arch::mips::__msa_srlr_w
source · pub unsafe fn __msa_srlr_w(a: v4i32, b: v4i32) -> v4i32
🔬This is a nightly-only experimental API. (
stdsimd
#48556)Available on (MIPS or MIPS-64) and target feature
msa
and MIPS only.Expand description
Vector Shift Right Logical Rounded
The elements in vector a
(four signed 32-bit integer numbers)
are shifted right logical by the number of bits the elements in vector b
(four signed 32-bit integer numbers) specify modulo the size of the
element in bits.The most significant discarded bit is added to the shifted
value (for rounding) and the result is written to vector (four signed 32-bit integer numbers).